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Cisco 10000 Series Router Performance Routing Engine Installation
OL-3971-03
Product Overview
Within the Cisco 10000 series ESR, two PXF network processor ASICs are used, yielding four parallel
processing pipelines, each containing eight processors in a row.
Figure 2 Cisco 10000 Series ESR Forwarding Path Processor Array
In the array of processors in , hardware, microcode, and Cisco IOS software resources provide advanced,
high-touch feature processing on the Cisco 10000 series ESR. The allocation of features to XMCs in the
processor pipeline is flexible and continues to change as new features are added.
The PXF network processor architecture allows all 32 independent processors to work efficiently on
per-packet feature processing, yielding high throughput while still allowing substantial feature
processing.
By centralizing packet processing in the PRE, the Cisco 10000 series ESR architecture frees up space
on line cards, enabling high interface density, yet retaining the compact NEBS transmission equipment
form factor.
Route Processor
The second component of the PRE is the route processor (RP), a high-speed, conventional
microprocessor that has special interfaces to the forwarding path:
• A high-speed direct memory access (DMA) channel that is sends packets back and forth between
the FP and the RP. Packets such as route updates that are not processed by the FP are sent through
this link to the RP. Similarly, the RP sends packets by passing them to the FP for transmission to
line cards.
• The RP also has memory-mapped access to all of the state information used by the eXpress
microcontrollers (XMCs). The RP is responsible for configuring the tables and lists used by the
XMCs.
The RP also includes such standard Cisco IOS facilities as Flash memory, NVRAM for storing
configuration files, and Ethernet connections for network management. This familiar environment makes
possible a simple transition from existing Cisco IOS-based routers to the Cisco 10000 series ESR
platform.
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