Cisco 10005 Instalační příručka stáhnout pdf (Strana 3)

Cisco 10000 Series Router Performance Routing Engine Installation

OL-3971-03

Product Overview

Figure 1 Distributed Processing Architecture in the PRE

Redundant PREs

You can configure two PREs in a single chassis for redundancy. If the primary PRE fails, the secondary

PRE automatically takes over operation of the router. Because all the line cards are physically connected

to both the primary and secondary PREs, the failure of a single PRE does not require user intervention.

If a failure occurs, all line cards automatically reset to the redundant PRE.

With redundant PREs, the Cisco 10000 series ESR can survive even a catastrophic processor failure and

still maintain the highest levels of uptime and availability. Startup and running configurations of the

secondary PRE are synchronized with the primary PRE, ensuring the fastest possible cut-over time if the

primary PRE fails.

Forwarding Path

The Cisco 10000 series ESR forwarding path comprises a unique blend of hardware and microcoded

processors that yields high forwarding rates with considerable flexibility for future growth in packet

processing features.

The forwarding path is centered around a pair of Cisco-designed multiprocessor ASICs called parallel

express forwarding (PXF) network processors. Each PXF network processor provides a packet

processing pipeline consisting of 16 microcoded processors, arranged as multiple pipelines.

Each of the 16 processors in a PXF network processor is an independent, high-performance processor,

customized for packet processing. Each processor, called an eXpress microcontroller (XMC), provides

a sophisticated dual-instruction-issue execution unit, with a variety of special instructions designed to

execute packet processing tasks efficiently.

In addition to processing packets, XMCs have access to on-chip resources such as register files and

timers. They also have shared access to very large off-chip memories for storing state information, such

as routing tables and packet queues.

Within a single PXF network processor, the 16 XMCs are linked together in four parallel pipelines. Each

pipeline comprises four XMCs arranged as a systolic array, where each processor can efficiently pass its

results to its neighboring downstream processor. Four parallel pipelines are used, to increase throughput.

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